W3EG128M72ETSU335JD3中文资料

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W3EG128M72ETSU-D3

-JD3-AJD3

ADVANCED*

1GB – 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL

FEATURES

Double-data-rate architecture

DDR200, DDR266, DDR333 and DDR400

JEDEC design speci cation Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8)

Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Power supply:

VCC = VCCQ = +2.5V ± 0.2V (100, 133 and

166MHz)

VCC = VCCQ = +2.6V ± 0.1V (200MHz) JEDEC standard 184 pin DIMM package

Package height options: JD3: 30.48 mm (1.20”) AJD3: 28.70 mm (1.13”)

NOTE: Consult factory for availability of:

Lead-free products

Vendor source control option Industrial temperature option

* This product is under development, is not quali ed or characterized and is subject to change or cancellation without notice.

DESCRIPTION

The W3EG128M72ETSU is a 128Mx72 Double Data Rate SDRAM memory module based on 1Gb DDR SDRAM components. The module consists of nine 128Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system ap pli ca tions.

OPERATING FREQUENCIES

DDR400@CL=3

Clock SpeedCL-tRCD-tRP

200MHz3-3-3

DDR333@CL=2.5

166MHz2.5-3-3

DDR266@CL=2133MHz2-2-2

DDR266@CL=2.5

133MHz2.5-3-3

DDR200@CL=2100MHz2-2-2

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PIN CONFIGURATION

PIN#12345678910111213141516171819202122232425262728293031323334353637383940414243444546

SYMBOLVREFDQ0VSSDQ1DQS0DQ2VCCDQ3NCRESET#VSSDQ8DQ9DQS1VCCQNCNCVSSDQ10DQ11CKE0VCCQDQ16DQ17DQS2VSSA9DQ18A7VCCQDQ19A5DQ24VSSDQ25DQS3A4VCCDQ26DQ27A2VSSA1CB0CB1VCC

PIN#47484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192

SYMBOLDQS8A0CB2VSSCB3BA1DQ32VCCQDQ33DQS4DQ34VSSBA0DQ35DQ40VCCQWE#DQ41CAS#VSSDQS5DQ42DQ43VCCNCDQ48DQ49VSSNCNCVCCQDQS6DQ50DQ51VSSVCCIDDQ56DQ57VCCDQS7DQ58DQ59VSSNCSDASCL

PIN#93949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138

SYMBOLVSSDQ4DQ5VCCQDQS9DQ6DQ7VSSNCNCNCVCCQDQ12DQ13DQS10VCCDQ14DQ15CKE1VCCQNCDQ20A12VSSDQ21A11DQS11VCCDQ22A8DQ23VSSA6DQ28DQ29VCCQDQS12A3DQ30VSSDQ31CB4CB5VCCQCK0CK0#

PIN#139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184

SYMBOLVSSDQS17A10CB6VCCQCB7VSSDQ36DQ37VCCDQS13DQ38DQ39VSSDQ44RAS#DQ45VCCQCS0#CS1#DQS14VSSDQ46DQ47NCVCCQDQ52DQ53NCVCCDQS15DQ54DQ55VCCQNCDQ60DQ61VSSDQS16DQ62DQ63VCCQSA0SA1SA2VCCSPD

W3EG128M72ETSU-D3

-JD3-AJD3

ADVANCED

PIN NAMES

A0-A12BA0-BA1DQ0-DQ63CB0-CB7DQS0-DQS17CK0CK0#

CKE0, CKE1CS0#, CS1#RAS#CAS#WE#VCCVCCQVSSVREFVCCSPDSDASCLSA0-SA2VCCIDNC

RESET#

Address input (Multiplexed)Bank Select AddressData Input/OutputCheck bits

Data Strobe Input/OutputClock InputClock input

Clock Enable inputChip Select InputRow Address StrobeColumn Address StrobeWrite EnablePower Supply

Power Supply for DQSGround

Power Supply for ReferenceSerial EEPROM Power SupplySerial data I/OSerial clock

Address in EEPROMVCC Indenti cation FlagNo ConnectReset Enable

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W3EG128M72ETSU-D3

-JD3-AJD3

ADVANCED

FUNCTIONAL BLOCK DIAGRAM

元器件交易网http://doc.guandang.net

W3EG128M72ETSU-D3

-JD3-AJD3

ADVANCED

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to VSSVoltage on VCC supply relative to VSSStorage TemperaturePower DissipationShort Circuit Current

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

SymbolVIN, VOUTVCC, VCCQTSTGPDIOS

Value– 0.5 ~ 3.6–1.0 ~ 3.6– 55 ~ +150

950

UnitsVV°CWmA

DC CHARACTERISTICS

0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V (100, 133 and 166MHz), VCCQ = 2.6V ± 0.1V (200MHz)

ParameterSupply VoltageSupply VoltageReference VoltageTermination VoltageInput High VoltageInput Low VoltageOutput High Voltage Output Low Voltage

SymbolVCCVCCQVREFVTTVIHVILVOHVOL

Min2.32.31.151.15VREF + 0.15– 0.3VTT + 0.76—

Max2.72.71.351.35VCCQ + 0.3VREF – 0.15

—VTT – 0.76

UnitVVVVVVVV

CAPACITANCE

TA = 25°C, f = 1MHz, VCC = 2.5V ± 0.2V (100, 133 and 166MHz), VCCQ = 2.6V ± 0.1V (200MHz)

Parameter

Input Capacitance (A0-A12)Input Capacitance (RAS#,CAS#,WE#)Input Capacitance (CKE0,CKE1)Input Capacitance (CK0,CK0#)Input Capacitance (CS0#,CS1#)Input Capacitance (DQM0-DQM8)Input Capacitance (BA0-BA1)

Data input/output Capacitance (DQ0-DQ63)(DQS)Data input/output Capacitance (CB0-CB7)

SymbolCIN1CIN2CIN3CIN4CIN5CIN6CIN7COUTCOUT

Max2929295.52982988

UnitpFpFpFpFpFpFpFpFpF

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W3EG128M72ETSU-D3

-JD3-AJD3

ADVANCED

IDD SPECIFICATIONS AND TEST CONDITIONS

0°C ≤ TA ≤ 70°C, VCC = VCCQ = 2.5V ± 0.2V (100, 133, 166MHz), VCC = VCCQ = +2.6V ± 0.1V (200MHz)

DDR400@ CL=3

ParameterOperating Current

SymbolConditionsIDD0

One device bank; Active - Precharge; (MIN); DQ,DM an …… 此处隐藏：23500字，全部文档内容请下载后查看。喜欢就下载吧 ……