DSP_lect02.1_xilinx_FPGA

DSP课件

微电子学院The theory and application of digital signal processing system本科(大三)

Lecture 2 XILINX FPGA Device& ToolsYang Li yangli@http://www.77cn.com.cn yangli@ic sjtu edu cn School of Microeletronics Shanghai Jiao Tong Univerisity

Spring 2010 S i

2010.春

DSP课件

OutlineFPGA structure and design flow Xilinx Virtex-II resource overview Virtex II Xilinx DSP system Design Flow Overview

DSP课件

FPGA - A Box of DSP BlocksAn FPGA can be viewed as a repository of DSP components waiting to be connected together.

Design Verify V if Place and Route

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Generic FPGA ArchitectureRow interconnects

Column interconnects

DSP课件

FPGA Design FlowDesign EntryDesign Verification g Functional Simulation Design Synthesis Static Timing Analysis

Many pieces of software participate in the design flow; The engineer can control and influence all stages of the process via constraints and options; The final bitstream configures every part of the device required for the implemented design. p g

Design Implementation Optimization FPGAs Mapping Placement Routing CPLD Fitting Bitstream Generation Back Annotation

Timing Simulation

Download to FPGA

In-Circuit Verification 5

DSP课件

Xilinx Vi t Xili Virtex-II P FPGA A hit t II Pro ArchitectureHigh-level, generic view of Hi h l l i i f the Xilinx Virtex-II Pro family; As device size increases, so does th amount of available d the t f il bl resources such as embedded multipliers, processors and configurable l i fi bl logic; The CLBs (Configurable Logic Blocks) form the main programmable fabric of the bl f b i f th device; DCMs (Digital Clock Managers) solve clock management issues

DSP课件

Xilinx Virtex II CLB Virtex-IICLB= C fi Configurable L i bl Logic Block

CLB One slice can implement a 2 bit full 2-bit adder, Four slices in one CLB can implement two independent 4bit full adders adders.7

Inside a slice

DSP课件

Xilinx Virtex II Slice Virtex-IIInside one slice upper half The majority of user-design functionality will be implemented by the slices; The primary measure of Xilinx FPGA device size is the number of slices in the chip; The 4-input LUTs can be used to implement logic; LUTs can be used as distributed RAM as well– extremely useful for DSP p p purposes. LUTs also can be used as ShiftRegisters– say, used as delay lines i t d of using registers. li instead f i i t LUT= Look-Up Table

lower half

DSP课件

Xilinx Virtex II Slice Virtex-II The registers implement sequential logic; Th multiplexers and CY The lti l d components can be used for routing signals through the slice; The AND gate at the bottom is used to implement efficient p multiplication.

DSP课件

Virtex-II Virtex II Slice (one half) (one-half)one slice half slice

Elements and connections are configured by the software tools g y and downloaded to device in bit stream. The bit stream will also configure the connection between slices and CLBs, etc.10

DSP课件

Xilinx Virtex II Block RAM Virtex-II Xilinx Virtex-

II devices have Virtex II dedicated 18 Kb Block RAMs throughout the device; One of the largest Virtex-II Pro (XC2VP125) has 556 Block RAMs and so 556 * 18= 10,008 Kb of Block RAM in total; Block RAM can be written at device configuration time or written/read during operation; Block RAM can be single or dual port (one address gives 2 pieces of data.)11

DSP课件

Xilinx Virtex II Distributed RAM Virtex-IIA LUT can store 16 bits and can be used as a 16x1 RAM; Two LUTs can form one 32x1 single-port RAM or one single port 16x1 dual port RAM - i.e. the same address produces data from both RAMs; This flexibility allows several single/ dual port RAM configurations of the 128 bits available within one CLB (4 slices * 2 LUTs * 16 bits= 128) A Virtex-II Pro with 55,616 Virtex II 55 616 slices therefore has 55,616 * 2 LUTs * 16 bits= 1,738 Kb of Distributed RAM;12

The ability to create small RAMs anywhere on the device is t i extremely useful - especially l f l i ll for DSP purposes

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Virtex-II Virtex II Embedded Multipliers Embedded multipliers are arranged in columns between CLBs; Multipliers are 18 x 18 bit and are p associated with BlockRAM for easy access to data; C b combinatorial or pipelined Can be bi i l i li d running at over 300MHz; MAC engines can be implemented by combining embedded multipliers with accumulators using LUTs; Cascade multipliers to implement multiplications with larger width.

DSP课件

What a designer needs to do ...Xilinx& M th Xili Mathworks provide a very good tool k id dt l set: Simulink, System Generator, and the ISE too s tools. A DSP designer only worries about:Is the arithmetic correct? (overflows, underflows, saturations, etc) t ti t ) Is the latency (delay) acceptable? Can we clock at a higher rate? g Can the synthesized result be placed and routed? Can we find another design using less hardware? What FPGA device do we need?

The tools will give us lots of support for these.

DSP课件

XILINX DSP system D i t Design Fl Flow Overview O i1) C Create a Design in Si t D i i Simulink U i li k Using Xili Xilinx Libraries (you may virtually draw a design.) 2) Simulate in Simulink 3) Generate HDL Code& Generate Testbench ( (using SysGen) g y ) 4) Perform RTL Simulation (ModelSim) 5) Synthesize HDL Code Place Route 6) Program the FPGA Device (download bitstream) 7) Vie ing waveforms, etc. (b ChipScope Viewing a efo ms etc (by Analyzer)

DSP课件

System Generator Design FlowIn the l b I th lab we will design f ill d i from S t System Generator G t and then implement to FPGA device, making sure that we test and verify on the way!MATLAB/SimulinkHDL System G …… 此处隐藏：3684字，全部文档内容请下载后查看。喜欢就下载吧 ……